• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for manufacturing electronic chips containing low dispersion components comprising the steps of: mapping the average dispersion of said components as a function of their position in semiconductor test slices; associating with each component (C) of each chip auxiliary correction elements (C, C1, C2, C3); activate by masking the connection of the correction elements to each component according to the initial mapping.
    公开号:FR3053156A1
    申请号:FR1656020
    申请日:2016-06-28
    公开日:2017-12-29
    发明作者:Francois Tailliet；Guilhem Bouton
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    COOSANT WITH LOW DISPERSION IN AN ELECTRONIC CHIP
    Field
    The present application relates to the field of manufacturing electronic components such as integrated circuits, and more particularly the present application aims to achieve within a semiconductor wafer components having a low dispersion relative to each other.
    Statement of Prior Art
    Integrated electronic circuits are generally manufactured from semiconductor wafers in which a large number of identical electronic chips are formed which are then separated from each other, usually by sawing.
    The manufacture of electronic chips comprises numerous masking steps, particular operations being performed according to the patterns of each mask, for example implantations of dopants, etchings of layers, and electrical connections in connection layers.
    In conventional manner, it can be seen that the electronic chips of a wafer contain elementary components such as capacitors, transistors and memory points which exhibit certain characteristic dispersions as a result of manufacture. In particular, a given component does not always have the same value from one semiconductor wafer to another, nor from one chip to another of the same semiconductor wafer.
    In some cases, these dispersions are extremely critical, for example when trying to manufacture tuning capacitors.
    To overcome these dispersions, numerous solutions have been used in the prior art, such as:
    Imposing extremely rigorous constraints on the manufacturing process: this is expensive and the limit of dispersion reached is generally only around ± 7% inside a slice; sorting the chips obtained and rejecting the bad chips: this can lead to yield losses greater than 10% if all the chips for which there is a dispersion greater than ± 5% are rejected; and / or at the end of manufacturing laser adjustments: this is of course an expensive and time consuming technique.
    Thus, processes are being sought which make it possible to reduce the production dispersion of electronic circuit chips in order to increase manufacturing yields and to avoid additional steps (sorting, laser adjustment, etc.). summary
    Thus, an embodiment provides a method of manufacturing electronic chips containing low dispersion components comprising the steps of: mapping the average dispersion of said components as a function of their position in test semiconductor slices; associating with each component (C) of each chip auxiliary correction elements (C, Cl, C2, C3); activate by masking the connection of the correction elements to each component according to the initial mapping.
    According to one embodiment, the components are capacitors and the correction elements are capacitors sharing an electrode with the main capacitor.
    According to one embodiment, the capacitors are formed between two layers of doped polycrystalline silicon and are provided with a dielectric consisting of a succession of layers of oxide, nitride and silicon oxide.
    According to one embodiment, the method provides photo-repetition masking steps, one of the reticles being intended to ensure or not the connections of the auxiliary components, and wherein said reticle is shifted by a variable step in addition to the not normal photo-repetition.
    One embodiment provides a semiconductor wafer containing electronic chips, each chip comprising at least one component of a first type, this component being associated with auxiliary correction components connected or not depending on the position of the chip in the wafer.
    According to one embodiment, the components of the first type are capacitors and the auxiliary components of the auxiliary capacitors sharing an electrode with the main capacitor and having surfaces much smaller than that of the main component, these auxiliary capacitors being connected or not depending on the position of the chip in the slice.
    According to one embodiment, the capacitors are ONO type.
    One embodiment provides an integrated circuit chip obtained by cutting a wafer as above. Brief description of the drawings
    These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures among which: FIG. 1 represents the value of tuning capacitors arranged in various chips of a slice depending on the distance of these chips in the center of the slice; Figure 2 illustrates a capacity adjustment strategy on a slice; Fig. 3 shows a first embodiment of a dispersion compensated capacitor structure; FIG. 4 represents the appearance of phototo-repeated patterns on a silicon wafer; and Figure 5 shows a second embodiment of a dispersion compensated capacitor structure. detailed description
    The same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed.
    In the present description, to facilitate understanding, we will first consider only the particular case where it is sought to achieve tuning capacitors whose dielectric is an oxide-nitride-silicon oxide tricouche and whose opposite electrodes are in highly doped polycrystalline silicon. Such capacitors will be referred to herein as ONO capacitors and may for example be used as tuning capacitors of an RF circuit. However, it should be noted that this is not the only application of the method described here.
    The inventors have studied the dispersion of ONO capacitor capacitors conventionally manufactured in a semiconductor wafer.
    FIG. 1 represents, on the ordinate, capacitance values C and on the abscissa the distance r with respect to the center of the semiconductor wafer of each chip in which at least one ONO capacitor is manufactured. It can be seen that if, for example, the value of the capacitance is 70 pF in the center of the chip, it decreases to a value of about 63 pF at the periphery of the chip. This example is given in the case of a slice with a diameter of 200 mm (8 inches).
    Figure 2 shows successive concentric zones of a semiconductor wafer. Note that, if all ONO capacitors are to have the same value of 70 pF in the center and periphery of the wafer, it is desirable, in the context of the example of FIG. 1, to keep capacitors such as which in the center (Add 0), add 1 pF (Add Ip) to the capacitors in the first ring, 2 pF (Add 2p) to the capacitors in the next ring, 3 pF (Add 3p) to the capacitors in the first ring next ring, 4 pF (Add 4p) to the capacitors in the next ring, 5 pF (Add 5p) to the capacitors in the next ring, 6 pF (Add 6p) to the capacitors in the next ring, and 7 pF (Add 7p) to the capacitors located in the last ring. Of course, this division into seven zones is given only as an example. One could choose a finer division (more zones) or a coarser division (fewer zones).
    As illustrated in FIG. 3, it is proposed here to make each capacitor as having a single lower plate 10 and several upper plates C, Cl, C2, C3. The lower and upper plates are for example doped polycrystalline silicon. The upper plate C has a clean surface to obtain, in the center of a slice, a main capacitor C of desired capacity, 70 pF in the example given here. In this example, the upper plates C1, C2, C3 correspond to auxiliary capacitors having respectively capacities of 4, 2 and 1 pF.
    A first connection metallization 11 extends between a contact with the lower plate 10 and a node A of the capacitor. Connection metallizations 12, 13, 14 and 15 extend between contacts on each of the upper plates C, Cl, C2 and C3 and pads 22, 23, 24, 25. The pads 22, 23, 24, 25 s extend over a metallization 20 from which they are separated by a not shown insulating layer. The metallization 20 is connected by a connection to a second node of the capacitor.
    Depending on whether the contact pads 23, 24, 25 are contacted with metallization 20, capacitors C and / or C2 and / or C3 may be added to capacitor C in order to be able to add values ranging from 1 to 7 pF at the base capacitor. This is done by masking. For all the pads 23-25, a via 33-35 is formed or not between each of the pads and the metallization 20. All the pads 22 are connected to the metallization 20 via a via 32. It will be noted that the fact that the upper plates auxiliary capacitors C1, C2, C3 are always present, whether they are connected or not, makes it possible to rationalize the fabrication, all the capacitors of the wafer being made in the same way. Only the mask corresponding to a step of defining vias 33-35 is modified according to the zone of the slice in which the capacitor is located. The example given above is particularly simple and corresponds to the case where a single mask is used to manufacture all the chips of a slice. It will be noted that various embodiments may be chosen to parallel at least one of the capacitors C1, C2, C3 with the capacitor C. For example, the connections 13-15 may be interrupted or not.
    In fact, photorepetition processes are generally used to manufacture integrated circuits: masks or reticles are manufactured and these reticles are moved from one area to another of the wafer.
    Each of the squares illustrated in FIG. 4 corresponds to the size of the reticle which will be photo-repeated. Each square generally comprises several chips, for example 1000. The squares corresponding to each of the annular zones of FIG. 2 will contain capacitors of the same values and this value will be shifted from the center to the periphery of the wafer according to the zones (Add 0). (Add Ip) (Add 2p), (Add 3p), (Add 4p), (Add 5p), (Add 6p), and (Add 7p) described in connection with Figure 2.
    One problem is that when photorepetition is performed, all the reticle patterns are identical since the reticle can not be changed from one photorepetition to the next.
    FIG. 5 illustrates an exemplary implementation of the correction connections of auxiliary capacitors. In the example of FIG. 5, four capacitors C, Cl, C2, C3 and the rear conductive plate 10 connected as previously by a metallization 11 to a node A (first electrode of the capacitor) have been represented. The metallizations 12, 13, 14 and 15 connected to each of the upper conductive layers of the capacitors C, Cl, C2, C3 are connected, as shown by way of example, to a series of pads arranged parallel to each other. The connection 12 is connected to a single elongate pad 51. The connection 13 is connected to one of two elongate pads 61 and 62 extending over half the length of the pad 51. The connection 14 is connected to two alternating pins. four studs 71, 72, 73, 74 of half length that of the pads 61 and 62 and extending parallel thereto. The last connection 15 to the capacitor C3 is connected to four alternates of eight pads 81-88. These pads are based on elongate metallization strips 91, 92, 93, 94 interconnected by a metallization 95 corresponding to the terminal B of the capacitor.
    There is shown by a line of vertically aligned black squares an example of locations to which the pads are connected or not by vias metallization formed below them. The stud 51 is always connected by a contact (a black square) to the underlying metallization, that is to say that the terminal B always takes into account the capacitor C. In the example shown, the stud 61, connected to the metallization 13, is also connected to the underlying metallization 92, that is to say that the capacitor C1 is connected in parallel to the capacitor C. The stud 72 is arranged in a location such that it is not connected to the metallization 14. This means that the capacitor C2 is not arranged in parallel on the capacitors C and Cl. On the other hand, the stud 83 is connected to the underlying metallization, this stud being connected to the metallization 15. Thus, the capacitor C3 is connected in parallel with the capacitor C. Consequently, in this example, only the capacitors C, Cl and C3 are connected in parallel, that is to say, in the context of the given numerical example, which is added to the capacitance C 4 + 1 pF (capacitance values Cl and C3).
    It will be understood that, depending on the horizontal shift of the vias line, all the values between 0 and 7 pF can be added to the capacitance of the capacitor C. This is a specific mask that governs the positions of the vias lines and it is possible in a photo-repetition process to slightly shift the photo-repetition distance between two successive photorepetitations. This makes it possible to shift the vias lines. The offset step can be only 100 nm in today's advanced technologies.
    There is shown an example in which this shift of the vias lines is a horizontal shift, it will be understood that one could choose other configurations using vertical offsets or combinations of horizontal and vertical offsets. Thus, it is possible to obtain ONO capacitors which all have the same value both at the center and periphery of a semiconductor wafer. This is achieved without adding any additional manufacturing steps, but only in the example given above by slightly shifting the position of a mask during a photo-repetition process.
    As indicated at the beginning of the present description, a particular example has been given in which ONO capacitors, for example tuning capacitors in a radio frequency circuit, are produced. The inventors have observed that the type of constant dispersion between the center and the periphery of a semiconductor wafer described with reference to FIG. 1 is present for other components. Such a dispersion may exist for MOS transistors, for memory points, for capacitors other than ONO capacitors, for example MOS capacitors, or MIM capacitors (metal-insulator-metal). In the case of MIM capacitors, the distribution of capacitor values is substantially the same on a wafer (varying from center to periphery) as in the case of ONO capacitors. The inventors have found that in other components the distribution may be different.
    Thus, the present invention generally provides a method of manufacturing an electronic chip containing low dispersion components comprising the following steps of mapping the average dispersion of said components according to their position in semiconductor test slices; associate each element of each chip with correction elements; and connect by masking the correction elements to each component according to said initial mapping.
    It will also be understood that the present invention applies to other masking processes than those described herein.
    权利要求:
    Claims (8)
    [1" id="c-fr-0001]
    A method of manufacturing electronic chips containing low dispersion components comprising the steps of: mapping the average dispersion of said components as a function of their position in semiconductor test slices; associating with each component (C) of each chip auxiliary correction elements (C, Cl, C2, C3); activate by masking the connection of the correction elements to each component according to the initial mapping.
    [2" id="c-fr-0002]
    The method of claim 1, wherein the components are capacitors and the correction elements are capacitors sharing an electrode (10) with the main capacitor.
    [3" id="c-fr-0003]
    3. The method of claim 2, wherein the capacitors are formed between two layers of doped polycrystalline silicon and are provided with a dielectric consisting of a succession of layers of oxide, nitride and silicon oxide.
    [4" id="c-fr-0004]
    4. Method according to any one of claims 1 to 3, wherein the manufacturing method provides photo-repetition masking steps, one of the reticles being intended to ensure or not the connections of the auxiliary components, and wherein said reticle is shifted by a variable step in addition to the normal step of photo-repetition.
    [5" id="c-fr-0005]
    5. Semiconductor wafer containing electronic chips, each chip comprising at least one component of a first type, this component being associated with auxiliary correction components connected or not depending on the position of the chip in the wafer.
    [6" id="c-fr-0006]
    Slice according to Claim 5, in which the components of the first type are capacitors and the auxiliary components of the auxiliary capacitors share an electrode (10) with the main capacitor and have surfaces much smaller than that of the main component, these auxiliary capacitors. being connected or not depending on the position of the chip in the slot.
    [7" id="c-fr-0007]
    7. Slice according to claim 6, wherein the capacitors are ONO type.
    [8" id="c-fr-0008]
    8. Integrated circuit chip obtained by cutting a wafer according to any one of claims 5 to 7.
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    法律状态:
    2017-05-22| PLFP| Fee payment|Year of fee payment: 2 |
    2017-12-29| PLSC| Publication of the preliminary search report|Effective date: 20171229 |
    2018-05-25| PLFP| Fee payment|Year of fee payment: 3 |
    2020-05-20| PLFP| Fee payment|Year of fee payment: 5 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1656020A|FR3053156B1|2016-06-28|2016-06-28|LOW DISPERSION COMPONENT IN AN ELECTRONIC CHIP|
    FR1656020|2016-06-28|FR1656020A| FR3053156B1|2016-06-28|2016-06-28|LOW DISPERSION COMPONENT IN AN ELECTRONIC CHIP|
    CN201611023603.9A| CN107546143B|2016-06-28|2016-11-21|Low delta component in an electronic chip|
    CN201621244897.3U| CN206271699U|2016-06-28|2016-11-21|Semiconductor crystal wafer and IC chip comprising electronic chip|
    US15/380,894| US10043741B2|2016-06-28|2016-12-15|Low-dispersion component in an electronic chip|
    US16/033,109| US11244893B2|2016-06-28|2018-07-11|Low-dispersion component in an electronic chip|
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